2012-12-30 14:08:13Morris
[VHDL] 垃圾推積區-計數器
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JK正反器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jkflipflop is
port(
Clock: in std_logic := '0';
PRN: in std_logic := '1';
CLRN: in std_logic := '0';
J : in std_logic := '0';
K : in std_logic := '0';
Q : out std_logic := '0';
NQ : out std_logic := '1'
);
end entity jkflipflop;
architecture rtl of jkflipflop is
signal Qt : std_logic;
begin
PROCESS(Clock,PRN,CLRN)
BEGIN
IF (CLRN = '0') THEN
Qt <= '0';
ELSIF (PRN = '0') THEN
Qt <= '1';
ELSIF (FALLING_EDGE(Clock)) THEN
IF (J = '0' and K = '0') THEN
Qt <= Qt;
ELSIF (J = '0' and K = '1') THEN
Qt <= '0';
ELSIF (J = '1' and K = '0') THEN
Qt <= '1';
ELSIF (J = '1' and K = '1') THEN
Qt <= not Qt;
END IF;
END IF;
END PROCESS;
Q <= Qt;
NQ <= not Qt;
end rtl;
計數器
library ieee;
use ieee.std_logic_1164.all;
entity syncounter is
port(
Clock: in std_logic := '0';
VDD : in std_logic := '1';
CLRN: in std_logic := '0';
Qa : out std_logic := '0';
Qb : out std_logic := '0';
Qc : out std_logic := '0';
Qd : out std_logic := '0'
);
end entity syncounter;
architecture rtl of syncounter is
component jkflipflop
port (
Clock: in std_logic := '0';
PRN: in std_logic := '1';
CLRN: in std_logic := '0';
J : in std_logic := '0';
K : in std_logic := '0';
Q : out std_logic := '0';
NQ : out std_logic := '1'
);
end component jkflipflop;
signal tQa : std_logic := '0';
signal tQb : std_logic := '0';
signal tQc : std_logic := '0';
signal tQd : std_logic := '0';
signal tQaANDtQb : std_logic := '0';
signal tQaANDtQbANDtQc : std_logic := '0';
begin
u0 : jkflipflop
port map (
Clock => Clock,
PRN => VDD,
CLRN => CLRN,
J => VDD,
K => VDD,
Q => tQa
);
u1 : jkflipflop
port map (
Clock => Clock,
PRN => VDD,
CLRN => CLRN,
J => tQa,
K => tQa,
Q => tQb
);
u2 : jkflipflop
port map (
Clock => Clock,
PRN => VDD,
CLRN => CLRN,
J => tQaANDtQb,
K => tQaANDtQb,
Q => tQc
);
u3 : jkflipflop
port map (
Clock => Clock,
PRN => VDD,
CLRN => CLRN,
J => tQaANDtQbANDtQc,
K => tQaANDtQbANDtQc,
Q => tQd
);
tQaANDtQb <= tQa and tQb;
tQaANDtQbANDtQc <= tQaANDtQb and tQc;
Qa <= tQa;
Qb <= tQb;
Qc <= tQc;
Qd <= tQd;
end rtl;
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