2012-12-30 14:12:49Morris
[VHDL] 垃圾堆積區-移位器除頻器
D1.png
除頻器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity divider is
port(
Clock: in std_logic := '0';
CLRN: in std_logic := '0';
CC : out std_logic := '0'
);
end entity divider;
architecture rtl of divider is
signal Qt : std_logic_vector(24 downto 0) :=
"0000000000000000000000000";
begin
PROCESS(Clock,CLRN)
BEGIN
IF (CLRN = '0') THEN
Qt <= "0000000000000000000000000";
ELSIF (RISING_EDGE(Clock)) THEN
Qt <= Qt + 1;
END IF;
END PROCESS;
CC <= Qt(24);
end rtl;
移位器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity parallelout is
port(
Clock: in std_logic := '0';
CLRN: in std_logic := '0';
A : in std_logic := '0';
B : in std_logic := '0';
Qa : out std_logic := '0';
Qb : out std_logic := '0';
Qc : out std_logic := '0';
Qd : out std_logic := '0';
Qe : out std_logic := '0';
Qf : out std_logic := '0';
Qg : out std_logic := '0';
Qh : out std_logic := '0'
);
end entity parallelout;
architecture rtl of parallelout is
component divider is
port(
Clock: in std_logic := '0';
CLRN: in std_logic := '0';
CC : out std_logic := '0'
);
end component divider;
signal Q : std_logic_vector(7 downto 0) :=
"00000000";
signal AandB : std_logic := '0';
signal Action : std_logic := '0';
begin
u0 : divider
port map (
Clock => Clock,
CLRN => CLRN,
CC => Action
);
AandB <= A and B;
PROCESS(Action,CLRN)
BEGIN
IF (CLRN = '0') THEN
Q <= "00000000";
ELSIF (RISING_EDGE(Action)) THEN
Q <= Q(6 downto 0) & AandB;
END IF;
END PROCESS;
Qa <= Q(0);
Qb <= Q(1);
Qc <= Q(2);
Qd <= Q(3);
Qe <= Q(4);
Qf <= Q(5);
Qg <= Q(6);
Qh <= Q(7);
end rtl;
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