Morris' Blog

2012-11-29 21:15:48Morris

[VHDL] 垃圾堆積區-加法器

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半加器

library ieee;
    use ieee.std_logic_1164.all;

entity ha is
port(
    a: in std_logic;
    b: in std_logic;
    c: out std_logic;
    s: out std_logic
);
end entity ha;

architecture rtl of ha is
    signal w_s : std_logic;
    signal w_c : std_logic;

begin
    w_s <= a xor b;
    w_c <= a and b;

    s <= w_s;
    c <= w_c;
end rtl;

全加器

library ieee;
use ieee.std_logic_1164.all;

entity fa is
port(
    a : in std_logic;
    b : in std_logic;
    ci : in std_logic;
    s : out std_logic;
    co : out std_logic
);
end entity;

architecture rtl of fa is
component ha is
    port (
      a : in std_logic;
      b : in std_logic;
      c : out std_logic;
      s : out std_logic
    );
end component;

signal w_c0 : std_logic;
signal w_s0 : std_logic;
signal w_c1 : std_logic;
signal w_s1 : std_logic;

begin
u0 : ha
port map (
    a => a,
    b => b,
    c => w_c0,
    s => w_s0
);

u1 : ha
port map (
    a => ci,
    b => w_s0,
    c => w_c1,
    s => w_s1
);
s <= w_s1;
co <= w_c0 or w_c1;
end rtl;

四位元加法器

library ieee;
use ieee.std_logic_1164.all;

entity cra is
port (
    a : in std_logic_vector(3 downto 0);
    b : in std_logic_vector(3 downto 0);
    s7_s : out std_logic_vector(6 downto 0)
);
end entity;

architecture rtl of cra is
component fa
    port (
      a : in std_logic;
      b : in std_logic;
      ci : in std_logic;
      s : out std_logic;
      co : out std_logic
    );
end component fa;

component seg7dec is
    port (
      a : in std_logic_vector(3 downto 0);
      op : out std_logic_vector(6 downto 0)
    );
end component seg7dec;

signal w_s : std_logic_vector(3 downto 0);
signal w_c : std_logic_vector(3 downto 0);

begin
u0 : seg7dec
port map (
    a => w_s,
    op => s7_s
);

u1 : fa
port map (
    a => a(0),
    b => b(0),
    ci => '0',
    s => w_s(0),
    co => w_c(0)
);

u2 : fa
port map (
    a => a(1),
    b => b(1),
    ci => w_c(0),
    s => w_s(1),
    co => w_c(1)
);

u3 : fa
port map (
    a => a(2),
    b => b(2),
    ci => w_c(1),
    s => w_s(2),
    co => w_c(2)
);
u4 : fa
port map (
    a => a(3),
    b => b(3),
    ci => w_c(2),
    s => w_s(3),
    co => w_c(3)
);
end rtl;

七段顯示器

library ieee;
    use ieee.std_logic_1164.all;

entity seg7dec is
port (
    a : in std_logic_vector(3 downto 0);
    op : out std_logic_vector(6 downto 0)
);
end entity seg7dec;

architecture rtl of seg7dec is
signal w_code : std_logic_vector(6 downto 0);

begin
    op <= not w_code;

    with a select
    w_code <= "0111111" when "0000",
              "0000110" when "0001",
              "1011011" when "0010",
              "1001111" when "0011",
              "1100110" when "0100",
              "1101101" when "0101",
              "1111101" when "0110",
              "0000111" when "0111",
              "1111111" when "1000",
              "1101111" when "1001",
              "1110111" when "1010",
              "1111100" when "1011",
              "0111001" when "1100",
              "1011110" when "1101",
              "1111001" when "1110",
              "1110001" when others;
end rtl;

測試所有可能的程式碼

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;

entity tb_cra is
end entity tb_cra;

architecture rtl of tb_cra is
component cra
    port (
      a : in std_logic_vector(3 downto 0);
      b : in std_logic_vector(3 downto 0);
      s7_s : out std_logic_vector(6 downto 0)
    );
end component;

signal tp : std_logic_vector(7 downto 0) := "00000000";
signal ta : std_logic_vector(3 downto 0);
signal tb : std_logic_vector(3 downto 0);
signal ts : std_logic_vector(6 downto 0);

signal period : time := 100 ns;
begin
u0 : cra
port map (
    a => ta,
    b => tb,
    s7_s => ts
);

ta <= tp(7 downto 4);
tb <= tp(3 downto 0);
tp <= tp + '1' after period;

end rtl;

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Morris' Blog

[VHDL] 垃圾堆積區-加法器

你可能感興趣的文章

我覺得很可以

欲成大樹 莫與草爭

規劃安排亂世中的小日子

最後第53天

欲成大樹莫與草爭