Morris' Blog

2012-12-16 20:39:00Morris

[VHDL] 垃圾堆積區-正反器

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RS正反器

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    
entity rsflipflop is
    port (
      Clock: in std_logic := '0';
      R: in std_logic := '0';
      S: in std_logic := '0';
      Q: out std_logic := '0';
      NQ: out std_logic := '1'
  );
end entity rsflipflop;

architecture rtl of rsflipflop is
  signal RnandClock : std_logic := '1';
  signal SnandClock : std_logic := '1';
  signal Qt : std_logic := '0';
  signal NQt : std_logic := '1';
begin
  RnandClock <= not (R and Clock);
  SnandClock <= not (S and Clock);
 
  NQt <= not (Qt and RnandClock);
  Qt <= not (NQt and SnandClock);
 
  NQ <= NQt;
  Q <= Qt;
end;
  

JK正反器
library ieee;
    use ieee.std_logic_1164.all;
   
entity jkflipflop is
  port (
    Ct : in std_logic := '0';
    J : in std_logic := '0';
    K : in std_logic := '0';
    Q : out std_logic := '0';
    NQ : out std_logic := '1'
  );
end entity jkflipflop;

architecture rtl of jkflipflop is
  component rsflipflop
    port (
      Clock: in std_logic := '0';
      R: in std_logic := '0';
      S: in std_logic := '0';
      Q: out std_logic := '0';
      NQ: out std_logic := '1'
    );
  end component rsflipflop;
  signal nClock : std_logic := '0';
 
  signal u0_Q : std_logic := '0';
  signal u0_NQ : std_logic := '1';
 
  signal Qt : std_logic := '0';
  signal NQt : std_logic:= '1';
 
  signal Jt : std_logic := '0';
  signal Kt : std_logic := '0';
begin
  nClock <= not Ct;
  Kt <= Qt and K;
  Jt <= NQt and J;
  u0 : rsflipflop
  port map(
      Clock => Ct,
      R => Kt,
      S => Jt,
      Q => u0_Q,
      NQ => u0_NQ
  ); 
  u1 : rsflipflop
  port map(
      Clock => nClock,
      R => u0_NQ,
      S => u0_Q,
      Q => Qt,
      NQ => NQt
  );
 
  NQ <= NQt;
  Q <= Qt;
end rtl;
 
測試 JK正反器

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use std.textio.all;
   
entity tb_jkflipflop is
end entity tb_jkflipflop;

architecture rtl of tb_jkflipflop is
    component jkflipflop
      port (
        Ct : in std_logic := '0';
        J : in std_logic := '0';
        K : in std_logic := '0';
        Q : out std_logic := '0';
        NQ : out std_logic := '1'
      );
  end component jkflipflop;
 
  signal tClock : std_logic := '0';
  signal tJ : std_logic;
  signal tK : std_logic;
  signal tQ : std_logic;
  signal tNQ : std_logic;
 
  signal period : time := 100 ns;

begin
  u0 : jkflipflop
  port map (
    Ct => tClock,
    J => tJ,
    K => tK,
    Q => tQ,
    NQ => tNQ
  );

  tClock <= not tClock after 50 ns;
 
  TPATTERN : process
  begin
    tK <= '0';
    tJ <= '1';
    wait for period;
    tK <= '0';
    tJ <= '0';
    wait for period;
    tK <= '1';
    tJ <= '0';
    wait for period;
    tK <= '0';
    tJ <= '0';
    wait for period;
    tK <= '1';
    tJ <= '1';
    wait for period;
    -- 1
    tK <= '1';
    tJ <= '0';
    wait for period;
    tK <= '0';
    tJ <= '0';
    wait for period;
    tK <= '1';
    tJ <= '0';
    wait for period;
    tK <= '0';
    tJ <= '1';
    wait for period;
    tK <= '1';
    tJ <= '0';
    wait for period;
    tK <= '1';
    tJ <= '1';
    -- 2
    tK <= '0';
    tJ <= '1';
    wait for period;
    tK <= '0';
    tJ <= '0';
    wait for period;
    tK <= '0';
    tJ <= '1';
    wait for period;
    tK <= '1';
    tJ <= '0';
    wait for period;
    tK <= '0';
    tJ <= '1';
    wait for period;
    tK <= '1';
    tJ <= '1';
    wait for period;   
    -- 3
    tK <= '1';
    tJ <= '1';
    wait for period;
    tK <= '0';
    tJ <= '0';
    wait for period;
    tK <= '1';
    tJ <= '1';
    wait for period;
    tK <= '0';
    tJ <= '1';
    wait for period;
    tK <= '1';
    tJ <= '1';
    wait for period;
    tK <= '1';
    tJ <= '0';
    wait for period;
  end process;
end rtl;
     
全加器 carry look ahead

library ieee;
    use ieee.std_logic_1164.all;

entity cla is
  generic(
    dw : integer := 4
  );
  port(
   cla_i_a : in std_logic_vector((dw-1) downto 0);
   cla_i_b : in std_logic_vector((dw-1) downto 0);
   cla_i_ci: in std_logic;
   cla_o_s : out std_logic_vector((dw-1) downto 0);
   cla_o_co: out std_logic
  );
end entity cla;

architecture rtl of cla is
    signal w_p : std_logic_vector((dw-1) downto 0);
    signal w_g : std_logic_vector((dw-1) downto 0);
    signal w_s : std_logic_vector((dw-1) downto 0);
    signal w_c : std_logic_vector(dw downto 0);

begin
  cla_o_s <= w_s;
  cla_o_co <= w_c(dw);
 
  w_p <= cla_i_a xor cla_i_b;
  w_g <= cla_i_a and cla_i_b;
  w_s <= w_p xor w_c((dw-1) downto 0);
 
  clau: process(w_p, w_g, w_c, cla_i_a, cla_i_b, cla_i_ci)
  begin
      w_c(0) <= cla_i_ci;
      for i in 0 to (dw-1) loop
        w_c(i+1) <= w_g(i) or (w_c(i) and w_p(i));
      end loop;
  end process;
end rtl;


 四位元乘法器
library ieee;
    use ieee.std_logic_1164.all;
entity asmul is
    generic(
      mdw : integer := 4
    );
    port(
      a : in std_logic_vector((mdw-1) downto 0);
      b : in std_logic_vector((mdw-1) downto 0);
      s1 : out std_logic_vector(6 downto 0);
      s2 : out std_logic_vector(6 downto 0)
    ); 
end entity asmul;

architecture rtl of asmul is
  component cla is
  generic(
    dw : integer := 4
  );
  port(
    cla_i_a : in std_logic_vector((dw-1) downto 0);
    cla_i_b : in std_logic_vector((dw-1) downto 0);
    cla_i_ci: in std_logic;
    cla_o_s : out std_logic_vector((dw-1) downto 0);
    cla_o_co: out std_logic
  );
  end component cla;
 
  component seg7dec is
  port (
    a : in std_logic_vector(3 downto 0);
    op : out std_logic_vector(6 downto 0)
  );
  end component seg7dec;
 
  type matrix is array((mdw-1) downto 0) of std_logic_vector((mdw-1) downto 0);
  signal w_atmp : matrix;
  signal w_btmp : matrix;
  signal w_ctmp : std_logic_vector((mdw-1) downto 0);
  signal w_stmp : std_logic_vector(((mdw*2)-1) downto 0);

begin
  mul_andu:process(a, b)
  begin
    for i in 0 to (mdw-1) loop
      for j in 0 to (mdw-1) loop
          w_atmp(i)(j) <= a(i) and b(j);
      end loop;
    end loop;
  end process;
 
  w_ctmp(0) <= '0';
  w_btmp(0) <= w_atmp(0);
 
  mulu: for i in 1 to (mdw-1) generate
      clau: cla
      generic map(
        dw => mdw
      )
      port map(
        cla_i_a => w_ctmp(i-1)&w_btmp(i-1)((mdw-1) downto 1),
        cla_i_b => w_atmp(i),
        cla_i_ci => '0',
        cla_o_s  => w_btmp(i),
        cla_o_co => w_ctmp(i)
      );
  end generate;
 
  mul_sumu: process(w_btmp, w_ctmp(mdw-1))
  begin
    for i in 0 to (mdw-1) loop
        w_stmp(i) <= w_btmp(i)(0);
    end loop;
    w_stmp((mdw*2-1) downto mdw) <= w_ctmp(mdw-1)&w_btmp(mdw-1)((mdw-1) downto 1);
  end process;
 
  u0 : seg7dec
  port map (
    a => w_stmp(3 downto 0),
    op => s1
  ); 
  u1 : seg7dec
  port map (
    a => w_stmp(7 downto 4),
    op => s2
  );
end rtl;
       
許胖 2012-12-18 23:32:30

<(_ _)>

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